Power semiconductor devices based on IGFET (insulated gate field effect transistor) cells are typically vertical devices with a load current flow between a first surface at a front side of a semiconductor die and a second surface at a rear side. In a blocking mode, stripe-shaped compensation structures extending from the front side into the semiconductor die deplete semiconductor mesas formed between the stripe-shaped compensation structures. The compensation structures allow higher dopant concentrations in the semiconductor mesas without adverse impact on the blocking capabilities. Higher dopant concentrations in turn reduce the on state resistance of the device. Typically, termination structures shape end portions of the semiconductor mesas at the edge of a cell field including the IGFET cells in a way that the doping to be depleted at the end portions is approximately equal to the doping depleted in a central portion of the cell field.
It is desirable to provide semiconductor devices with low ohmic losses and non-problematic avalanche characteristics.